The present invention generally relates to the field of Design Automation of semiconductor VLSI chips, and more particularly, to a method and a system providing an efficient statistical timing analysis of cycle time independent tests.
An objective of a conventional statistical static timing analysis (SSTA) is to prevent circuit limited yield (CLY) losses by accounting the effects of parametric variability upon switching time distributions of various signals within a digital circuit. SSTA can be performed at a transistor level or at a gate level, using pre-characterized library elements including those at higher levels of abstraction for complex hierarchical chips.
SSTA algorithms are known to operate by way of a first levelizing the logic structure, and breaking any loops in order to create a directed acyclic graph (timing graph). Modern designs can often contain millions of placeable objects, with corresponding timing graphs having millions or tens of millions of nodes. For each node, a corresponding arrival time (AT), transition rate (slew), and required arrival time (RAT) are computed for both rising and falling transitions as well early and late mode analysis. Each value can be represented in general as a distribution, i.e., using a first-order canonical form, wherein timing quantities are represented as functions of underlying sources of variation, as described e.g., in U.S. Pat. No. 7,428,716 to Visweswariah, of common assignee. The arrival time (AT) distribution represents the latest or earliest time at which a signal can transition due to the entire upstream fan-in cone. Similarly, the required arrival time (RAT) distribution represents the latest or earliest time at which a signal must transition due to timing constraints in the entire downstream fan-out cone.
The ATs are propagated forward in a levelized manner, starting from the design primary input asserted (i.e., user-specified) arrival times, and ending at either the primary output ports or the intermediate storage elements. In single fan-in cases, AT sink node=AT source node+delay from source to sink.
Whenever multiple signals merge, each fan-in contributes a potential arrival time computed as AT sink (potential)=AT source+delay, making it possible for the maximum (late mode) or minimum (early mode) of all potential arrival times to be statistically computed at the sink node. Typically, an exact delay function for an edge in a timing graph is not known, but instead only the range of possible delay functions can be determined between some minimum delay and a maximum delay. In this case, maximum delay functions are used to compute the late mode arrival times and minimum delay functions used to compute the early mode arrival times.
A timing test (e.g., setup or a hold check) involves a comparison of arrival times in order to determine if the proper ordering relationships between the corresponding signals are satisfied. Such a comparison of AT values produces a quantity known as slack, which when positive in sign indicates that the timing test has been satisfied (and the margin thereof), whereas a negative value indicates a failing test and potential problem.
Timing tests can be broadly categorized as either clock cycle time dependent or cycle time independent. Cycle time dependent tests are those whose slack is computed as a function of clock cycle time(s). By contrast, cycle time independent tests are those wherein the computed slack value is invariant to underlying clock cycle time(s). Typically, but not always, setup tests are cycle time dependent, as a full clock cycle (or the greatest common divisor of clock cycles) is allowed for an arrival time to propagate from launching to a receiving latch, and therefore, the slack depends on the cycle time(s) of the launch and the capture clocks. Similarly, it is typical for hold tests to be cycle time independent. The aforementioned, however, does not always hold true for setup and hold tests, as various adjusts can be present in the timing graph. For example, in the case of a user specified timing adjust (e.g., equal to a full clock cycle, or a greatest common divisor [GCD] of clock cycles), a setup test can end up becoming a cycle time independent test, and/or a hold test can become cycle time dependent.
In the case of some high-performance digital integrated circuits, at-speed screening is performed, and manufactured products are binned into multiple frequency categories. In such circumstances, during the digital implementation phase, timing engineers can be particularly interested in ensuring that parametric variation does not result in a circuit limited yield (CLY) loss for cycle time independent timing tests. As such, CLY issues can present chip-kill problems that are present regardless of the lowering of the clock frequency. On the other hand, when such screening and binning manufactured products by frequency is possible, the timing engineers can be willing to accept the possibility of CLY loss at a particular target cycle time for cycle time dependent timing tests since the underlying circuits can be able to operate correctly at one of the lower clock frequency bins. In the above situation, it is often the case that timing engineers desire a means to perform SSTA and report the results for cycle time independent tests only.
One prior technique for performing SSTA analysis of cycle time independent tests has traditionally involved a first propagation of full timing data on the entire timing graph (i.e., propagating early and late timing values regardless of whether a value is needed in a downstream cycle time independent test), using an inflated cycle time. The purpose of the inflated cycle time is to move the cycle time dependent tests to a positive slack value, such that only tests which are frequency independent can show up as a negative slack requiring attention from a SSTA closure perspective. However, there are inherent inefficiencies with the prior art when using an inflated cycle time. Most importantly, a full AT and RAT propagation is still required throughout the entire design, regardless of whether a timing quantity is of interest, i.e., needed at a timing test which is frequency independent. This leads to an excessive amount of wasted calculation and an increasing runtime which negatively impacts designer productivity.
In another prior art technique, SSTA is performed on a timing graph (propagating early and late timing values regardless of whether a value is needed in a downstream test), and is followed by generating reports which are filtered based on the test type. For example, using such prior art methods, a timing engineer can select only report hold tests (and exclude setup tests) in order to determine whether there are any violations among cycle time independent tests. The use of filtering of reporting, however, can miss cycle time independent setup cases (such as those involving a user specified timing adjust, as previously described), and can report hold tests which are cycle time independent (e.g., similarly, in a case involving a user specified timing adjust). Furthermore, filtering reports suffers from the same problem of wasted calculations as described above with respect to the prior art method of inflating clock cycle time.
In summary, in a high performance chip design there is a desire to perform statistical timing for the purpose of analyzing frequency independent tests, whereas frequency dependent tests are handled by a separate “nominal” timing run. This differentiation is presently supported by performing a statistical timing run with cycle time uplift such that the cycle time dependent tests have large slack values. The cycle time uplift approach is both cumbersome and leads to wasteful calculation of many statistical timing quantities that are not needed (when such quantities only feed the frequency dependent tests).
Accordingly, there is a need to provide a method and a system capable to achieve an efficient statistical timing analysis of cycle time independent tests.